Pipelined digital-to-analog converter

ABSTRACT

A pipelined digital to analog converter is disclosed which utilizes a series of three capacitor and switch sections to convert a three bit segment of a digital word into an analog voltage. For a ten bit digital word, three 3-capacitor sections would be required with an additional capacitor section. The voltage across the output, or last, capacitor is the analog voltage in direct relation to the input digital word. Each of the three capacitor sections works in relation to switched transistors to charge and discharge in a predetermined fashion said capacitors, in relation to the binary level of each of the three digits in the input digital word. The circuit operates from the least significant bit to the most significant bit, and converts the input digital word to an output analog voltage.

This invention relates to a digital to analog converter wherein a series of three capacitor and transistor switch sections convert three bit segments of a digital word to an analog voltage which is pipelined to successive sections wherein the voltage across the last capacitor is, in fact, an analog representation of the applied digital signal.

BACKGROUND OF THE INVENTION

Most conventional techniques for digital to analog conversion require both high performance analog circuitry, such as operational amplifiers, and digital circuitry for counting, sequencing, and data storage. This has tended to result in hybrid circuits consisting of one or more bipolar analog integrated circuit chips and an MOS chip to perform the digital function. High performance and fairly complex signal processing has recently become possible on a single monolithic chip due to the fact that very accurate capacitor ratios could be obtained in MOS technology to replace cumbersome conventional techniques such as diffused resistors, complex thin film process, or ion implanted resistors. One problem with existing integratd circuits is that the area of silicon occupied by capacitors increases exponentially as a function of the number of input bits. Hence, in the prior art it has been difficult to get enough accuracy for ten bit resolution with reasonable silicon area. Also, for high speeds (say, 10⁷ conversions/second) the amplifiers may not be fast enough.

The present invention discloses a series of three capacitor and switch sections to convert a three bit segment of a digital word. For a ten bit digital word, for example, three 3-capacitor sections would be required with an additional capacitor section. The voltage across the output, or last, capacitor is the analog voltage in direct relation to the input digital word. Each of the three capacitor sections works in relation to switched transistors to charge and discharge, in a predetermined fashion, said capacitors, in relation to the binary level of each of the three digits in the input digital word. The circuit operates from the least significant bit to the most significant bit, and converts the input digital word to an output analog voltage.

DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the invention, reference may be had to the following detailed description of the invention in conjunction with the drawings wherein:

FIG. 1 is a schematic diagram of the digital to analog converter of the present invention showing two 3-capacitor sections; and

FIG. 2 is a schematic diagram of the sequence of timing signals applied to and utilized in the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 discloses a schematic diagram of a circuit which accomplishes the digital to analog conversion of the present invention, for 6-bit digital words. All capacitors are of equal size. Across the bottom of FIG. 1 can be seen capacitors C₀ through capacitor C₇. The next row up from the row of capacitors is a row of transistor switches Q₀ through Q₇. Each of these switch transistors is enabled by one of the timing signals Φ₁, Φ₂, or Φ₃. A row of switching transistors M₁ through M₁₂ selectively couples the circuit to the input binary digits under analysis. The PMOS transistor M₁ would be responsive to the first binary digit b₁ ^(k) if it was in the logic one state. The NMOS transistor M₂ would have the same first binary digit but be responsive to the logic zero state of this binary digit. The input to transistor M₁ is the voltage suply V_(R) which, as an example, may be 5 volts. The input to transistor M₂ is connected to ground potential. Thus, the source electrode of transistor M₁ is coupled to voltage V_(r), the gate electrode when Φ₁ is high is coupled to the input binary digit, while the drain electrode is coupled to the drain electrode of transistor M₂ and to the capacitor network as shown in FIG. 1. When Φ₁ is high, transistor M₂ 's gate electrode is coupled to the complement of the input binary digit, while the source electrode of transistor M₂ is connected to ground. The subsequent capacitor combinations are similar and will be described hereinafter.

When phase signal Φ₁ is applied to the circuit, none of the other two phase signals Φ₂ or Φ₃ are applied; thus they are non-overlapping timing signals. When timing signal Φ₁ is applied, transistor M₁ or M₂ would be enabled depending upon whether or not the input binary digit is a logic one or a logic zero. Also, upon the application of timing signal Φ₁, transistor switch Q₀ is closed and capacitor C₀ is coupled directly to ground through transistor Q₀, thus discharging it completely. Transistor switch Q₁ is open because timing signal Φ₂ has not yet been applied to transistor Q₁. Thus, at Φ₁ =1, if the binary digit applied is a logic one, then transistor switch M₁ is closed, M₂ remains open, and the supply voltage V_(R) is applied directly to and charges capacitor C₁. As stated above, transistor Q₁ is open because Φ₂ has not been applied; as is transistor Q₂ open because timing signal Φ₃ has not been applied. Thus, at this particular moment T, with a binary digit b₁ being in the logic one state, transistor M₁ is on, with V_(R) charging capacitor C₁ to V_(R), which in this instance may be 5 volts. The resulting charge in C₁ is q=C₁ V_(R).

While the rest of the description will be analyzed with all binary one digits applied, it can be seen, however, that if binary digit b₁ is a logic zero, transistor Q₀ would still be closed, capacitor C₀ would still be discharged to ground, transistors Q₁ and Q₂ would still be open because of the absence of timing signals Φ₂ and Φ₃, but now transistor M₂ would be directly coupled to ground thereby discharging capacitor C₁ to ground potential.

When timing signal Φ₁ turns off and a finite time elapses, timing signal Φ₂ is now applied, see FIG. 2. Transistor Q₀ opens, transistor Q₁ closes, transistor Q₃ remains open, capacitors C₀ and C₁ are now connected through transistor Q₁ in parallel and share their capacitive charge with each other. However, since C₀ had no charge while C₁ was charged to 5 volts, the charge on both C₀ and C₁ is now q/2. At this moment, assuming that bit b₂ is also a logic one, capacitor C₂ is charging to the supply voltage V_(R). Since at this moment timing signal Φ₃ is off, transistor Q₂ is open. Thus, at this particular time, the charge on capacitor C₀ is q/2, the charge on capacitor C₁ is q/2, while the charge on capacitor C₂ is equal to q.

Thus, the charge in the combined parallel capacitor combination of C₀ and C₁ is now q while the voltage is V_(R) /2=2.5 volts. The voltage on capacitor C₂ is equal to 5 volts at this moment. However, when timing signal Φ₂ turns off, capacitor C₁ is alone again with a voltage of 2.5 volts and a charge of q/2. Capacitor C₂ is also alone at this moment with a voltage of 5 volts and a charge of q.

When the next timing signal Φ₃ goes high, capacitors C₁ and C₂ are now connected in parallel for the first time. Thus, these capacitors, C₁ and C₂, share their charges as other capacitors share their charges above; so at this particular moment, the total charge of capacitors C₁ and C₂ is 3q/2, because the charge on capacitor C₁ is q/2 while the charge on capacitor C₂ is q, the total charge being 3q/2. Since each value of capacitance for capacitors C₀ through C₆ is the same, the voltage on each of the capacitors C₁ and C₂ is now the average of the 2.5 volts and the 5 volts, or combined voltage of 3.75 volts. Next, phase signal Φ₃ would go low leaving the 3.75 volt signal level on capacitor C₂. Now, when timing signal Φ₁ goes high again, the charge on capacitor C₂, that is 3q/4, is shared with capacitor C₃ which is now charged to the charge q if the signal of bit 3 in the digital word is a logic 1. As above, the voltage on capacitor C₃ is 5 volts but when it shares its voltage with capacitor C₂, which above was seen to be 3.75 volts, the resultant voltage on capacitor C3 when timing signal Φ₁ goes low and C₃ is isolated will be reduced. The voltage at this point on capacitor C₃ would be the average of the 3.75 volts with the 5 volt signal or 4.375 volts at this particular moment. The charge is thus propagated along but is divided by two every time. Thus is introduced the weighting of the voltage by powers of 2. The formula for output voltage, for the case when all digits of the digital word equal 1, is therefore

    V.sub.0 =V.sub.R (1-2.sup.-N)

where N is the number of bits b_(i). Thus, for a 4 bit word the resultant output analog voltage for a 4 bit word of all logic 1's would be 4.6875 volts; while for an 8 bit word the output analog voltage for all 1's in the 8 bit word would be approximately 4.98 volts. The voltage would decrease down to zero linearly for a combination of input binary digits of all logic zeroes. In the general case, the formula giving the output voltage is

    V.sub.0 =(V.sub.R /2)(b.sub.N +2.sup.-1 b.sub.N-1 +. . . +2.sup.-N+1 b.sub.1).

Each of the three capacitor sections could have the input bits applied simultaneously and stored at the inputs to transistors M₁, M₂, M₃, M₄, M₅, or M₆, because the phase pulses Φ₁, Φ₂, and Φ₃ are sequential and non-overlapping. For a 10 bit converter, the circuit would comprise three 3-capacitor sections with an additional capacitor stage to equal 10 stages. It is the right most capacitor that has the output analog voltage on it. The last capacitor in FIG. 1 is designated C₆, but in general can be C_(N) for any number N of binary digits. If, however, the input digits were exactly six as shown in FIG. 1, capacitor C₆ would be the output capacitor.

The main advantage to the above circuit is that no amplifiers are needed which would slow down the operation. The circuit only uses the capacitors and the switching transistors as set forth in the Figure.

Since the circuit shown updates the output voltage across C_(N) only once in each 3 block cycles, 3 switched capacitor arrays, similar to that shown in FIG. 1 but operated by clock signals which are shifted by one clock interval from array to array, may be combined to realize a system which generates a new analog output signal in each clock interval.

It can be shown that clock feedthrough effects affect only the gain and the offset voltage, but not the linearity of the converter. This is acceptable in many applications.

While the invention has been described with reference to a specific embodiment, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the true spirit and scope of the invention. In addition, many modifications may be made without departing from the essential teachings of the invention. For instance, two reference voltages V_(R1) and V_(R2) may be used in FIG. 1 at the sources of M₁ -M₂, M₃ -M₄, etc., rather than V_(R) and ground. 

What is claimed is:
 1. A digital to analog converter comprising:a plurality of capacitor and transistor switch sections, each of said sections for converting three digits of a binary digital signal to an output analog voltage, each of said sections comprising: first, second, and third pairs of input switching transistors, wherein the first transistor in each said pair is enabled and transfers a predetermined reference voltage only in response to a logic one in the input binary digit, while the second transistor in each said pair is enabled and thus transfers a ground voltage only in response to a logic zero in the same input binary digit, first, second, and third output switching transistors coupled to said first, second, and third pairs of input switching transistors and responsive to first, second, and third independent and non-overlapping enabling signals, and first, second, and third equal size capacitors coupled to said first, second, and third output switching transistors and to ground potential, wherein said first, second, and third capacitors are selectively connected to said ground potential or said reference or ground voltage from said input pairs of switching transistors in response to said applied binary digits, said enabling signals being sequentially applied to said first, second, and third output switching means to discharge said capacitors and combine stored charges thereon, such that an analog voltage representative of said applied digital signal is produced and selectively moved from said capacitor to capacitor from the least significant bits to the most significant bits in said applied digital signal.
 2. The digital to analog converter as set forth in claim 1 wherein the output analog voltage is

    V.sub.0 =(V.sub.R /2)(b.sub.N +2.sup.-1 b.sub.N-1 +. . . +2.sup.-N+1 b.sub.1)

where V₀ is the output voltage, V_(R) is the reference voltage, and N is the number of input binary digits. 